Implant device and method of making the same

ABSTRACT

The invention provides chip packaging and processes for the assembly of retinal prosthesis devices. Advantageously, photo-patternable adhesive or epoxy such as photoresist is used as glue to attach a chip to the targeted thin-film (e.g., parylene) substrate so that the chip is used as an attachment to prevent delamination.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/838,788, filed Aug. 28, 2015 (allowed), which is acontinuation-in-part of U.S. patent application Ser. No. 13/830,272,filed Mar. 14, 2013, now issued as U.S. Pat. No. 9,144,490 on Sept. 29,2015, which claims priority to U.S. Patent Application No. 61/640,569,filed Apr. 30, 2012, the disclosures of which are hereby incorporated byreference in their entirety for all purposes.

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH OR DEVELOPMENT

This invention was made with government support under EEC0310723 awardedby the National Science Foundation. The government has certain rights inthe invention.

FIELD OF INVENTION

This invention relates to biomedical implants in general and inparticular to biomedical implants that employ a parylene substrate thatallows the total connection and fabrication of a biomedical implantcomprising semiconductor chips or other pre-manufactured electricalcomponents such as transistors, resistors, capacitors or inductors.

BACKGROUND OF THE INVENTION

One of the biggest challenges that a prosthetic implant has to overcomeis the reliable packaging of integrated circuit (IC) chips withbio-devices to withstand corrosive body fluids. This is especially truefor complex neural implants and retinal implants because hundreds of orthousands of electrodes may be needed to be connected to the necessaryIC chips (see, K. D. Wise et al., International Conference of theEngineering in Medicine and Biology Society on Neural Engineering 2007,pp. 398-401). In comparison, a pacemaker has only one stimulatingchannel and a cochlear implant requires only 5 to 6 stimulatingelectrodes to be able to regain hearing capabilities of an impairedpatient (see, K. Najafi et al., IEEE Conference on Nano/Micro Enginneredand Molecular Systems, 2004, pp. 76-97). In addition, in order to avoidpossible infection and medical complications, it is desirable to haveprosthetic devices completely inside a subject's body. This means thattechnologies for integration, connection and packaging of IC chips forhigh-lead-count implant devices are of high demand. As shown previously,aligned electrical connection can be done between parylene-C interfacesand high density multi-channel chips by a conductive epoxy squeegeetechnique (see, Jay H. C. Chang, Ray Huang, and Y. C. Tai, Proc.TRANSDUCERS 2011, pp. 378-381), where a PDMS mold was used to house theIC chips and serve as the safety squeegee buffer zone. However, it istoo big to be implanted inside a human eyeball (1˜2 cm³) (see, M.Humayun et al., Vision Research, 43 (2003), pp. 2573-2581). In addition,since the adhesion only relied on conductive epoxy contacting less than2% of the total connection area, delamination could easily happen wheneven a small force was applied to the assembled devices. This would beespecially serious during surgery. Since the next generation intraocularretinal prosthetics require the whole device, including coils,electrodes, stimulation chip and other ASICs to be fitted inside a humaneyeball, the device must be further designed in terms of both size andsurgical complexity.

Parylene-C has become a popular material for BioMEMS implantapplications due to its superior properties (see, J. H. Chang et al,Proc. TRANSDUCERS 2011, pp. 390-393; J. H. Chang et al, Proc. NEMS 2011,pp. 1067-1070). It has also served as an intermediate layer for siliconwafer bonding (see, H. Noh et al, J. Micromech. Microeng. 14(2004), 625;H. Kim et al., J. Microelectromech. Syst. 14(2005), 1347-1355). However,the bonding between parylene-C and silicon is still problematic.

There are various processes for packaging integrated circuit (IC) dice.Some packaging techniques contemplate the creation of electronic modulesthat incorporate multiple electronic devices (e.g. integrated circuits,passive components such as inductors, capacitor, or resisters) into asingle package. Despite the advances of the prior art, and althoughimplantable devices have been developed with micro-electrical-mechanicalsystem (MEMS) technology, there is a need for better packagingtechnology, especially for high-lead-count retinal and neural implants.The present invention provides these and other needs.

BRIEF SUMMARY OF THE INVENTION

The present invention provides substrates, methods and processes toassemble IC chips to thin-film substrates such as a parylene substratesfor medical implants such as retinal implants. Advantageously, theinventive packaging technology can be used to produce 10,000 or moreconnections within an area as small as 36 mm², a chip size reasonablefor retinal implants. The current invention provides methods forimproving packaging techniques.

As such, in one embodiment, the present invention provides a method forfabricating a thin-film substrate such as a parylene substrate forattachment of a device, comprising:

-   -   depositing a first thin-film layer such as a parylene layer on a        silicon-wafer to form a bottom thin-film layer;    -   depositing a metal to the bottom parylene layer to form an        electrical connection;    -   depositing a second thin-film layer such as parylene layer        adjacent to the metal to form a top thin-film layer and a        thin-film metal thin-film sandwich (e.g.,        parylene-metal-parylene sandwich);    -   providing a mask adjacent to the top thin-film layer; and    -   directing an etching beam onto the mask to fabricate the        thin-film substrate (e.g., parylene substrate) for attachment of        the device.

In another embodiment, the present invention provides the thin-filmsubstrate (e.g., parylene substrate) made by the inventive process. Thesubstrate is useful to integrate, connect and package IC chips forhigh-lead-count implant devices.

In order to validate this technology, chips designed with 268connections to mimic real IC chips under development were used for themeasurement of connection yield. In addition, after squeegee connectionand encapsulation by a thick parylene-C coating, the connected chipsunderwent accelerated soaking tests in a high temperature salinesolution. The results show that the technique provides exceptionallyhigh connection yield.

In yet another embodiment, the present invention provides a method forassembling an integrated circuit to a thin-film substrate (e.g.,parylene substrate), comprising:

-   -   spin coating a photo-patternable adhesive or epoxy to an        integrated circuit (IC) to form a covered IC;    -   masking the covered IC; and    -   patterning the covered IC using photolithography to expose a        plurality of bonding pads on the IC chip to form a patterned IC        to integrate into the thin-film substrate (e.g., parylene        substrate).

In still another embodiment, the present invention provides abiocompatible thin-film (e.g., parylene) substrate for attachment of adevice, comprising:

-   -   a first thin-film (e.g., parylene) layer;    -   a metal adjacent to the first thin-film layer;    -   a second thin-film (e.g., parylene) layer adjacent to the metal        to form a thin-film metal thin-film sandwich (e.g.,        parylene-metal-parylene sandwich), wherein the second layer of        thin-film has an opening, the opening having at least one        electrical contact provided on an internal surface thereof, the        opening configured to accept at least one electrical circuit        device and to provide electrical communication between the at        least one electrical contact and the at least one electrical        circuit device, the biocompatible thin-film (e.g., parylene)        substrate configured to be implanted within a living organism        after accepting the at least one electrical circuit device.

In certain aspects, the device having at least one electrical circuit isan integrated circuit (IC) chip. In addition, in one aspect the devicesuch as an IC chip is integrated into the substrate by a conductiveepoxy squeegee electrical connection. Preferrably, the device isintegrated into the substrate by a photo-patternable adhesive orphotoresist used as a mechanical glue.

In another embodiment, the present invention provides:

-   -   a biocompatible package for low density connections, comprising:    -   a feedthrough layer;    -   an application specific integrated circuit (ASIC) face down on        the feedthrough layer;    -   a printed circuit board (PCB) attached to the ASIC adapted for        off-chip components and wire bonded to the feedthrough layer;    -   metal walls adjacent the feedthrough layer; and a metal lid to        encase and make the biocompatible package.

These and other aspects, objects, and embodiments will become moreapparent when read with the detailed description and figures whichfollow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1K show a fabrication process of a flexible parylene-Cconnection substrate and chip integration according to one embodiment ofthe present invention.

FIGS. 2A-2E show in FIG. 2A a schematic representation of the fabricatedflexible parylene-C substrate connected with a chip and discretecomponent. FIG. 2B shows the backside of the discrete component area.FIG. 2C shows a close-up view of the chip integration; FIG. 2D shows aretinal tack; FIG. 2E shows a schematic of an eye and integration of afabricated flexible parylene-C substrate connected with a chip.

FIGS. 3A-3B show a custom holder for chip assembly technique.

FIGS. 4A-4C show in FIG. 4A a dummy chip for assembly yield test; FIGS.4B-4C show pads also served as alignment marks.

FIGS. 5A-5D show in FIG. 5A unbaked AZ4620; FIG. 5B shows AZ4620 bakedat 140° C. for 30 minutes in a vacuum oven; FIG. 5C and FIG. 5D show theslope formed by reflow is beneficial for conductive epoxy to be fedthrough.

FIGS. 6A-6B show the gluing area was about 2% as is shown in FIG. 6A;FIG. 6B shows the gluing area increased to about 94% (2%+92%) by theextra photoresist used as glue.

FIG. 7 shows a schematic representation of a clamp as the bonding toolon the testing samples.

FIGS. 8A-8B show in FIG. 8A a cross-sectional SEM image of the bonding(2 MPa, 130° C.); FIG. 8B shows the adhesive interface after parylenepeeling.

FIGS. 9A-9C show in FIG. 9A the setup of the force gauge to measure thepeeling force. FIG. 9B shows a real testing sample after bonding; FIG.9C shows the schematic representation of the testing sample.

FIG. 10 shows the peeling force vs bonding temperature for variousphoto-patternable adhesives.

FIG. 11 shows the peeling force vs bonding pressure for variousphoto-patternable adhesives.

FIGS. 12A-12B shows in FIG. 12A the maximum peeling forces of differentphoto-patternable adhesives; FIG. 12B shows the peeling force vs bondingtime for different photo-patternable adhesives.

FIGS. 13A-13C show in FIG. 13A a surgical parylene-C device connectedwith silicon chip and discrete components; FIG. 13B and FIG. 13C showmetal pads are exposed with other area covered by adhesives.

FIG. 14 shows the setup of the measurement, wherein the electrode arrayoutputs (the electrode end that is placed on macula) were probed tocheck the connection.

FIG. 15 shows the connection yields under 4 different conditions;reliability tests were carried out after squeegee connection,encapsulation by parylene-C coating, and accelerated soaking in 90° C.saline.

FIGS. 16A-16D show in FIG. 16A dummy chips with 40 μm by 40 μm pad sizeand 40 μm separation; FIG. 16B shows the connection between a parylenesubstrate and dummy chip;

FIG. 16C shows the yield vs separation of pads; FIG. 16D shows the yieldvs side length of pads.

FIG. 17 shows one embodiment of a low density packaging technology.

DETAILED DESCRIPTION OF THE INVENTION I. Embodiments

The present invention relates to biomedical implants in general and inparticular to biomedical implants that employ a thin-film (e.g.,parylene) substrate that allows the total connection and fabrication ofa biomedical implant comprising semiconductor chips and/or otherpre-manufactured electrical components. In one embodiment, the presentinvention provides a method for fabricating a thin-film substrate suchas a parylene substrate for attachment of a device, comprising:

-   -   depositing a first thin-film layer such as a first parylene        layer on a silicon-wafer to form a bottom thin-film layer;    -   depositing a metal to the bottom thin-film (e.g., parylene)        layer to form an electrical connection;    -   depositing a second thin-film layer such as second parylene        layer adjacent to the metal to form a top thin-film layer and a        thin-film metal thin-film sandwich (e.g.,        parylene-metal-parylene sandwich);    -   providing a mask adjacent to the top thin-film layer; and    -   directing an etching beam onto the mask to fabricate the        thin-film substrate (e.g., parylene substrate) for attachment of        the device. The first thin-film layer can be the same or        different than the second thin-film layer. Although parylene is        the preferred substrate, a skilled artisan will appreciate that        the material can be other thin-film polymers such as polyimide,        Teflon, kapton, or a printed circuit board (PCB) and the like.        The remainder of the application will use parylene as an        illustrated example. Other thin-films can also be used.

In certain aspects, the present invention provides a fabrication process100 for a parylene-substrate, such as a flexible parylene-C substrate.In one exemplary embodiment, FIG. 1A shows a 5μm first parylene-C layer(bottom layer) 120 deposited on a silicon substrate 110 such as a HMDStreated silicon wafer, which aids in the device being detached such asbeing released in distilled or deionized water, preferably deionizedwater.

Next, as is shown in FIG. 1B, adjacent to the first parylene layer 120(bottom parylene layer) is a metal 130 such as a titanium/gold (Ti/Au)alloy for a metal lift-off. The metal provides an electrical connection.A second parylene layer 150 (top layer) such as a thicker parylene-C(about 40 μm) layer is then deposited to complete theparylene-metal-parylene sandwich structure as is shown in FIG. 1C. Theprocess includes providing a mask 160 such as a metal mask (e.g.,aluminum) deposited as a parylene-C etching mask to etch through thethick parylene-C layer as is shown in FIG. 1D. Finally, electrode sites170, 175 and device contour 180 are defined by reactive ion etching(such as a 2-step O₂ plasma etching as is shown in FIG. 1E) or deepreactive ion etching (DRIE) can be used. FIG. 1F shows the flex beingreleased from the wafer 110.

Although the foregoing example uses parylene-C, the processes andembodiments of the device herein are not so limited. Other parylenessuch as parylene N, C, D, HT, AM, A or combinations thereof can also beused. Parylene-C is the preferred parylene. Although parylene is thepreferred substrate, a skilled artisan will appreciate that the materialcan be other thin-film polymers such as polyimide, Teflon, Kapton, or aprinted circuit board (PCB) and the like.

Other materials useful for substrate and/or carrier design include, butare not limited to, silicon, glass, steel, G10-FR4, or any other FR4family epoxy, etc. In some embodiments, the silicon substrate is usedonly as a carrier during fabrication and is accordingly removed beforethe package is complete. In other embodiments, the carrier remains anintegral part of the package.

In certain aspects, the silicon-wafer used in the methods is treatedwith 1,1,1,3,3,3-hexamethyldisilazane (HMDS). A skilled artisan willappreciate other treatments can be used to release the parylenestructure from the silicon wafer.

In certain aspects, the first parylene layer 120 and the second parylenelayer 150 are deposited on the silicon substrate by chemical vapordeposition (CVD). The first layer has a thickness of between about 0.1μm to about 100 μm thick such as 10, 20, 30, 40, 50, 60, 70, 80, 90, or100 μm. Preferably, the thickness of the first parylene layer (bottomlayer) is between about 1 μm and about 10 μm thick such as about 1, 2,3, 4, 5, 6, 7, 8, 9, or 10 μm thick.

Typically the second parylene layer (top layer) 150 is thicker than thefirst parylene layer 120. In one instance, the second parylene layer isbetween 10 μm and 200 μm thick such as 10, 20, 30, 40, 50, 60, 70, 80,90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190 or 200 or eventhicker. Preferably, the second parylene layer is between 20 μm and 60μm thick such as about 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 30, 31,32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,50, 51, 52, 53, 54, 55, 56, 57, 58, 59 or 60 μm thick.

In certain aspects, the metal 130 used for the lift-off is atitanium/gold (Ti/Au) alloy. However, other suitable metals and alloysinclude, but are not limited to, Cr/Au, Ni/Au, Ti/Au, Al/Ti, Ag/Ti,Cr/Au/Ti/Ni/Au, Ni/Pd/Au, Ti/Ni/Au or combinations thereof. Those ofskill in the art will know of other metals useful for the presentinvention.

The process includes providing a mask such as a metal mask deposited asa parylene-C etching mask to etch through the second parylene-C layer.In general, etching is a reactive ion etching (RIE) masked by a metalmask. In addition, deep reactive etching can be used (DRIE). Othersuitable mask materials are also useful. The RIE can be oxygen plasmaetching.

A skilled artisan will appreciate that the parylene layers of theparylene devices described herein are not limited to two parylenelayers. In addition, the metal of the parylene device is not limited toa single metal. The parylene devices are based on a sandwich structure.As long as a metal is sandwiched by a top and a bottom parylene layer,there can be numerous layers stacked on the substrate. In addition,there can be a plurality of masks to open the electrodes and define thecontour of the device(s).

In certain instances, the process described is used to generate multipleparylene-metal-parylene sandwich layers on a carrier (e.g., a siliconwafer) such as a plurality of sandwich layers including 2, 3, 4, 5, 6,7, 8, 9, 10 or more parylene-metal-parylene sandwich layers. Althoughthe process just described generates 1 sandwich layer, a skilled artisanwill appreciate that the process can be repeated to make any number ofsandwich layers.

In still other aspects, the invention includes a parylene substrate madeby the processes herein. As is described in more detail below, theinvention provides attaching a device to the parylene substrate suchdevice includes, for example, an integrated circuit and other discretecomponents.

In one aspect, after the flex is released, an ASIC is integrated withthe released flex. For example, FIG. 1G shows the flex previouslyreleased from the wafer being aligned with the ASIC 185 with aphoto-patternable adhesive 182 placed in a mold 187. In FIG. 1H, theflex is bonded with ASIC 185 with PPA 182 and ready for conductive epoxy189 using a squeegee 188 process. As is shown in FIG. 1I, after aconductive epoxy squeegee process, some conductive epoxy residue 189 isleft on the top surface, which may cause a shortage. As is shown in FIG.1J, the top is cleaned to provide a cleaned top surface to avoidshortage. In FIG. 1J, the conductive epoxy 183 is kept inside cavitiesto make a connection between the flex and ASIC. FIG. 1K shows therelease of the assembly device from the mold.

In certain aspects, the inventive thin-film (e.g., parylene) substratehosts electronic components such as application specific integratedcircuits (ASICs), which are interconnected via metallization traces,such as about 3.7 μm wide metallization trace. In one embodiment, thefabricated flexible parylene-C substrate is connected with an IC chipand other discrete components. In certain other aspects, the substrateor micro-module of the present invention contains a variety ofcomponents including, but not limited to, one or more integratedcircuits, ASICs, interconnect layers, heat sinks, conductive vias,passive devices, MEMS devices, sensors, pre-manufactured electricalcomponents, transistors, resistors, capacitors, inductors, micropumpsand filters. The components are arranged and stacked within the modulein a wide variety of different ways. The layers and components of themodule can be deposited and processed using various conventional waferlevel processing techniques, such as spin coating, lithography and/orelectroplating.

The parylene package can include many other types of devices andcomponents than the ones illustrated. The package can also containalmost any number of active and/or passive devices. Examples of suchactive and/or passive devices includes resistors, capacitors,oscillators, magnetic cores, MEMS devices, sensors, cells, communicationdevices, integrated thin film battery structures, inductors, and thelike. These devices can be positioned and/or stacked in variouslocations within the package. The components may take the form ofprefabricated discrete components or may be formed in-situ. Oneadvantage of the lithography-based process used to create the presentpackage is that these and other components can be formed in-situ duringthe layered formation of the package. That is, while prefabricated,discrete components can be placed in almost any position within package,components can also be fabricated directly onto any photo-imageablelayer using any suitable technique, such as conventional sputteringand/or electroplating.

Turning now to FIG. 2A, a schematic representation 200 is shown of thefabricated flexible parylene-C substrate 210 connected with anintegrated chip 220 and discrete components e.g., capacitor 211 andoscillator 217. In certain aspects, the multi-electrode array 230 withoutputs 232 is placed on the macula of a human eye or an eye of anothermammal and can be fixed by a retinal tack 235 (FIG. 2D). In oneinstance, integrated discrete components are placed on or in an eyeball.FIG. 2B is the backside of the discrete component area. FIG. 2C shows aclose-up view of the chip integration. FIG. 2E is a schematic of an eyeshowing positioning of an electrode array 241, integrated ASICs 245 andan intraocular RF coil 250.

As shown in FIG. 2A, the discrete components such as for example acapacitor 211 and an oscillator 217 are mounted and connected byconductive epoxy to make an electrical connection. In certain instances,two incisions or suture holes are made for the device to be fixed in aneyeball 261, 265 (see, FIG. 2E). In one aspect, a multi-electrode array230 is placed on the macula and fixed by a retinal tack 235. FIG. 2Ealso shows the electrode array 241, inside one incision 261 and theintegration of the application specific integrated circuit 245 in theother incision 265. An intraocular RF coil 250 is also shown. Theinterconnection part is preferably about 0.1 mm to about 6 mm wide suchas about 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 3, 4, 5, or6 mm wide. In certain instances, the interconnection is about 2 mm wide.In certain instances, the interconnection depends on the incision sizefor surgery on the eyeball. However, in most instances, the width isabout 2 or 3 mm.

In certain instances, IC chips having high-density and multi-channelbonding pads (e.g., pad size smaller than about 100 μm×100 μm; pitchsmaller than about 200 μm) can be connected with a parylene substrate bya conductive epoxy squeegee technique. Other discrete components withlarger bonding pads, such as caps and oscillators, can be connected witha parylene substrate manually by conductive epoxy using needles. Powerand data coils with larger bonding pads can also be connected with aparylene substrate manually by conductive epoxy using needles. The wholeintegrated device is then fixed inside an eyeball by a retinal tack(e.g., close to electrode array).

In another embodiment, the present invention provides methods forintegrating the flexible parylene substrate with an IC chip and otherdiscrete components. The method includes chip pattern lithography,including photoresist spinning, baking, exposing, and developing as wellas integrating the IC chip into the flexible parylene substrate. Asshown in FIG. 3A, IC chip assembly can be done in a custom holder 300.

In operation, chips 310, 315, 320 are first secured in a holder 300, andall the chip pattern lithography, including photoresist spinning,baking, exposing, and developing is done in this holder in series. Afterchip integration with a parylene-C interface by a conductive epoxysqueegee connection, the chip 315 can be released from the back side ofthe mold, which is beneficial for the whole device to be implantedinside the eyeball. The chip can be integrated and packaged into theflexible parylene substrate. The processing of the IC chips to form apatterned IC chip is typically done on a custom chip pattern mold. FIG.3A also shows the mold can serve as a safety buffer zone for a squeegeeprocess. The size and the depth of the mold is designed to accommodatevarious sizes of the chip. FIG. 3B shows an expanded view of an IC chip.

In one example of a squeegee process of the present invention, acommercially available conductive epoxy is first mixed well and appliedon the surface of an edge of the parylene substrate. In certaininstances, the parylene substrate has pre-designed holes and/or wellsthat are etched during the fabrication process. The holes and/or wellsserve as a screen for this process after the IC chip is aligned andbonded well with the parylene substrate. A rubber squeegee is then usedto push the epoxy across the surface, so the epoxy fills the holesand/or wells in the parylene substrate, to electrically connect theparylene substrate and IC chip.

In certain instances, dummy chips with conductive traces are fabricatedto simulate the actual chip and special pads are pre-connected forconnection yield measurement. For example, FIG. 4A shows a dummy chipfor an assembly yield test. FIG. 4B shows pads can also serve asalignment marks. FIG. 4C shows a metal pad exposed with a resolution ofaround 5 μm being achieved.

The present invention provides methods and processes for alow-temperature bonding between a thin-film (e.g., parylene such asparylene C) and silicon using photo-patternable adhesives. This methodcan be used to determine the bonding pads and also reduce the residualstress in packaging. Advantageously, this low-temperature bonding allowsselectively local area bonding, without applying a high electric field.Thus it is especially suitable for the integration of a parylenesubstrate with microelectronics in MEMS packaging.

As such, in yet another embodiment, the present invention provides amethod for assembling an integrated circuit to a thin-film substrate.Although parylene is the preferred substrate, a skilled artisan willappreciate that the material can be other thin-film polymers such aspolyimide, Teflon, kapton, or a printed circuit board (PCB) and thelike. The method comprises:

-   -   spin coating a photo-patternable adhesive or epoxy to an        integrated circuit (IC) to form a covered IC;    -   masking the covered IC; and    -   patterning the covered IC using photolithography to expose a        plurality of bonding pads on the IC to form a patterned IC, for        integration into a thin-film (e.g., parylene) substrate.

In certain instances, the invention provides low-temperature bondingprocesses to facilitate the connection and packaging of variouscomponents for use as biomedical implants. In certain instances, thebonding technology can be used to facilitate the connection betweenparylene-C substrates and an IC as well as descrete components, whichsubstrates have pre-metalized electrical connections. The chips arepreferrably bound on the substrates with proper alignment so the metalpads on the parylene substrates and the metal pads on the chips line up.

In certain instances, commercially available photo-patternable materialssuch as photo-patternable adhesive or epoxy can be used. In certainaspects, the photo-patternable material is a photoresist. Suitablephotoresist includes SU-8, AZ4620, AZ1518, AZ4400, AZ9260, THB-126N,WPR-5100, BCB, polyimide and the like. The processing conditions arefacile with respect to bonding temperature, pressure, time, and surfacetreatment. The results show that for example, the epoxy-based SU-8 isvery effective with a peeling force up to 6.3 N.

In certain instances, AZ4620 photoresist is used in the processes due toexcellent reflow properties (P. J. Chen et al., J. Microelectromech.Syst, 17(2008), pp. 1352-1361). The patterned AZ4620 photoresist isbaked at 100° C. to about 180° C. such as 140° C. for 10 minutes to 80minutes such as about 30 minutes in vacuum oven and its smooth surfaceformed by reflow helps the conductive epoxy refill, as shown in FIG. 5A-D. The side lengths were almost the same before and after baking suchthat the reflown photoresist does affect conductivity by covering thewhole metal pad. In one specific embodiment, in no way limiting, FIG. 5Aillustrates unbaked AZ4620. FIG. 5B shows AZ4620 baked at 140° C. for 30minutes in a vacuum oven. FIGS. 5C and 5D show that the slope formed byreflow is beneficial for conductive epoxy to be fed through.Advantageously, the side lengths show no change before and after baking.

In previous applications, conductive epoxy was fed through the cavityembedded in a parylene-C substrate and relied on to make both electricaland mechanical connections. As shown in FIG. 6A, the prior art processuses only conductive epoxy 615 to connect the parylene substrate and thechip 602. The metal pad is shown as 625. In the process of the presentinvention, both conductive epoxy 615 and photo-patternable adhesive(e.g., photoresist) 610 such as AZ4620 is used. In fact, after applyingAZ4620 (as glue here) to the chip 602, the total gluing area betweenparylene-C substrate and a chip 602 is increased from 2% to 94%, asshown in FIG. 6B. In certain instances, the unnecessary pads were alsocovered to avoid shortage happening underneath the parylene-C interfaceduring a squeegee connection process.

The high-density connections between the chip and the parylene-Csubstrate were again done by conductive epoxy squeegee, while the customholder provided the safety buffer zone for squeegee to totally replacethe function of PDMS holders (see, Jay H. C. Chang, Ray Huang, and Y. C.Tai, Proc. NEWS 2011, pp. 1110-1113).

II. Low-temperature bonding between parylene-C and silicon

In certain instances, the photo-patternable adhesives are firstspin-coated on clean silicon wafers with for example, HMDS and oxygenplasma treatments, followed by standard photolithography process todefine the bonding pads. In certain preferred aspects, the methodsinclude baking the patterned IC to form a smooth surface. In certainother instances, the parylene substrate is first treated with oxygenplasma to enhance bonding with photo-patternable adhesives. In stillother instances, the IC chip is treated by HMDS and/or oxygen plasma toenhance bonding with photo-patternable adhesives.

Focusing on the application on chip integration, as an illustrativeexample of photo-patternable adhesives, SU-8 (13 μm and 28 μm), andAZ4620 (10 μm and 19 μm) are selected as an illustration to createsuitable aspect ratios of the cavity or opening. Other photoresistsinclude AZ1518, AZ4400, AZ9260, THB-126N, WPR-5100, BCB, polyimide andthe like.

As is shown in FIG. 7, a clean 30 μm parylene-C film 730 treated byoxygen plasma is then aligned with a diced wafer 740 and the structureis sandwiched by two glass slides 715, 725. A clamp 750 having two arms710, 720 is used as a bonding tool to make good contact and applyconstant force on the testing samples. The heating process is operatedin a vacuum oven and the maximum testing temperature is set to be about120-180 ° C. such as about 150° C. to prevent damage to the IC chips.

FIGS. 8A and 8B show one example of cross-sectional SEM images ofsamples bonded by photo-patternable adhesives. The bonding pads are welldefined with desired thickness and the shape of the microstructures isnot changed during the bonding process. Moreover, the flexibleintermediate adhesives does not cause residual stress after bonding.

In one aspect, the methods include first treating the parylene substratewith oxygen plasma treatment to enhancing bonding. Such plasma treatmentconditions include, for example, about 10 W to about 100 W such as about50 W; 100 mtorr to about 300 mtorr such as about 200 mtorr; and 0.1minute to about 5 minutes such as about 1 minute duration.

In certain instances, each of the plurality of bonding pads is between 1μm and 10 μm. In certain instances, the bonding pads can each bedifferent dimensions. The thickness of photo-patternable adhesives onthe IC chip is from 10 μm to 30 μm such as 10, 11, 12, 13, 14, 15, 16,17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 or 30 μm. In certaininstances, the patterned IC and a parylene substrate are assembled usingconductive epoxy or paste. The methods include delivering conductiveepoxy to make a high-density multi-channel IC chip connection by ahigh-throughput squeegee technique. In certain instances, thehigh-density multi-channel IC chip is greater than 1000 channels on a 25mm² chip area or even 10,000 channels on a 36 mm² or about 5-300channels per mm² chip area.

In certain aspects, when IC chips have a pitch size larger than about200 μm, applying conductive epoxy is performed with needles having adiameter smaller than 100 μm. As discussed above, the process on ICchips to form a patterned IC chip is done on a custom chip pattern mold.The mold serves as a safety buffer zone for the squeegee process. Thesize and the depth of the mold are designed to accommodate the size ofthe chip.

As is shown in FIG. 9A, the peeling force is measured by a force gaugesetup to investigate bonding strength. FIG. 9B shows a testing sampleafter bonding; FIG. 9C shows a schematic representation of the testingsample.

Each data point represents the average of five measurements. Force gaugeis fixed on a motorized stage to pull the partially peeled film at 90degree with a speed of 100 μm/s. Peeling force as a function of bondingtemperature is shown in FIG. 10.

FIG. 11 shows peeling force as a function of bonding pressure. Afteranalaysis, the results show that the higher the bonding temperature andpressure, the stronger the bonding.

Advantageoulsy, parylene-C film treated by oxygen plasma dramaticallyenhances the bonding for photo-patternable adhesive such as photoresists(e.g., SU-8) (see, Blanco F J et all., J. Micromech. Microeng. 14(2004), 1047-1056). SU-8 microstructure will not deform even underbonding pressure of 2 MPa where the maximum bonding forms. FIG. 12Ashows the maximum peeling force of different photopatternable adhesives.FIG. 12B shows the peeling forece versus bonding time for differentphoto-patternable adhesives. Z4620 can withstand pressure up to 0.5 MPa.In certain aspects, the bonding time has almost no effect on the bondingstrength when the samples are heated more than one hour.

As a demonstration, this technique is applied on a 268-channelconduction chip integrated with parylene-C surgical device for retinalimplant (FIG. 13). After patterning the adhesives on chips (see, J. H.Chang et al, Proc. MEMS 2012, pp. 353-356), the spatial resolution ofbonding pads built by SU-8 can be 5 μm. The bonding area is increasedfrom 2% to 94% and the measured connection yield is improved from 92% to98%.

This low-cost and low-temperature bonding process is proven to enablethe sealing of MEMS structures.

In another embodiment, the present invention provides a biocompatiblethin-film substrate. Although parylene is the preferred substrate, askilled artisan will appreciate that the material can be other thin-filmpolymers such as polyimide, Teflon, kapton, or a printed circuit board(PCB) and the like. The invention provides a thin-film (e.g., parylene)substrate for attachment of a device, comprising:

-   -   a first thin-film (e.g., parylene) layer;    -   a metal adjacent to the first thin-film (e.g., parylene) layer;    -   a second thin-film (e.g., parylene) layer adjacent to the metal        to form a thin-film metal thin-film (e.g.,        parylene-metal-parylene) sandwich, wherein the second layer of        parylene has an opening or cavity, the opening having at least        one electrical contact provided on an internal surface thereof,        the opening configured to accept at least one electrical circuit        device and to provide electrical communication between the at        least one electrical contact and the at least one electrical        circuit device, said biocompatible thin-film (e.g., parylene)        substrate configured to be implanted within a living organism        after accepting the at least one electrical circuit device.

In certain aspects, the device having at least one electrical circuit isan integrated circuit (IC) chip. In addition, the device such as an ICchip is integrated in the substrate by a conductive epoxy squeegeeelectrical connection. Preferrably, the device is integrated into thesubstrate by a photo-patternable adhesive used as a mechanical glue. Inone embodiment, the whole structure (e.g., the device having at leastone electrical circuit is an integrated circuit (IC) chip) isconformally coated and sealed with parylene-C (poly-para-xylylene-C),and if necessary, with medical grade epoxy to achieve totalencapsulation for biocompatibility.

In certain instances, once the device is implanted, there can becommunication with the implanted device and an external device.Communicaiton can be performed using either percutaneous connectors orwireless communication methods. Some of the kinds of signals that arecommunicated between the implanted device and an external device includepower signals and data signals. Power signals can include signals thatprovide power from an external power supply to an implanted device, sothat a battery present in the implanted device can be maintained in asuitable state of charge, or so that a battery can be eliminated fromthe implanted device. For some conventional devices having batteries,surgery may become necessary to replace the device because its batteryis expected to reach the end of its useful life. Any surgery poses ahealth risk and unnecessary surgery is best avoided if possible,especially in persons who already have health issues. Accordingly,implantable devices that do not have to be replaced because of a batteryare advantageous.

Data signals can include data signals from an external detector to animplanted device (such as providing an electrical signal correspondingto an audible signal received by a microphone to a cochlear implant forcommunication by way of a person's nervous system to the person'sbrain), control signals from an external detector to an implanted devicethat provide the ability to control the implanted device by using suchsignals (e.g., controlling the state of operation of the implanteddevice to meet the needs of the person), and data signals from theimplanted device to an external device to monitor the condition andoperation of the implanted device itself, to monitor the condition ofthe person (such as pulse rate, cardiac signals, or other signalsrelating to the condition being treated) and conditions in the vicinityof the implanted device (such as physiological signals, e.g.,temperature, pressure, pH), or to monitor the signals the implanteddevice is applying to the person. In some embodiments, data signals canbe used to “tune” or “reprogram” the implanted device to take advantageof improvements in understanding of the person's condition and theintervention, assistance, or treatment that the person should have, orprovide improvements in the implantable device operation and controlprocedures or operational software that are developed after the deviceis implanted.

Additional integrated circuits within package or module can be arrangedin a wide variety of ways and may be placed at other location within thepackage. By way of example, different integrated circuits may bepositioned in different photo-imageable layers and/or within the samelayer. In various embodiments, the integrated circuits can be stacked,positioned side-by-side, placed in close proximity to one another and/orbe separated by a substantial distance relative to the overall size ofpackage. Integrated circuits can also have a variety of different formfactors, architectures and configurations. For example, they may takethe form of relatively bare dice (e.g., unpackaged dice, flip chipsetc.), or partially and/or fully packaged dice.

III. Device Testing

The following operational tests illustrate the reliability experimentsto test the electrical connections of the parylene substrate.

FIG. 14 illustrates the setup 1400 for the test measurements. As showntherein, the electrode array outputs 1410, 1415 were probed to check theelectrical connections. In certain aspects, these electrodes are placedon the macula of a mammalian eye such as a human eye.

The setup 1400 includes a patterned chip 1428 and a parylene interface1433. Photoresist 1420 is sandwich between the wafer 1428 and theparylene 1430. In addition, metal 1425 is included between the wafer1428 and the photoresist 1420, or between the conductive epoxy 1418 andthe wafer. Electrically conductive vias are provided to electricallyconnect components (e.g., ICs/traces/contacts/passive components, etc.)that reside at different layers of the package. The vias are arranged toextend through various layers. By way of example, the vias may be usedto couple traces from two different interconnect layers together; a dieor another component to an interconnect layer; a contact to a trace, dieor other component, etc.

In one experiment, the connection yield right after squeegee wasmeasured by probing using 1440 and 1441, the stimulating electrodes.Afterwards, an additional thick parylene-C was coated on the entiredevice (except the output electrodes) to insulate and stabilize theconnection, and to protect the metals embedded in the parylene-Csubstrate from corrosive body fluids. The connection yield was recordedafter this coating. Finally, the device was soaked in 90° C. salinesolution for 5 days and the connection yield was again recorded.

The results in FIG. 15 show that the yield in operation of the inventivedevice under four different conditions. Reliability tests were carriedout after squeegee connection; soaking without encapsulation;encapsulation by parylene-C coating; and accelerated soaking in 90° C.saline. The results indicated that the processes combined with thickparylene-C coating for packaging does provide a high connection yield.

The results indicate that the new gluing technique is satisfactory(˜98%), while the yield without the new technique is significantly lower(˜88%). Moreover, for the connections without photoresist gluingtechniques, most of the disconnections happened at peripheral pads wheredelamination force is applied.

In addition, the limits of the pad size and separation between pads wereinvestigated. Chips with different pad separations and sizes weredesigned and fabricated for measurement.

FIG. 16A shows chips with 40 μm by 40 μm pad size and 40 μm separation.FIG. 16B shows connections between parylene substrate and a chip. FIG.16C shows yield vs separation of pads. FIG. 16D shows yield vs sidelength of pads. The results show that high connection yield (>90%) canbe achieved for pads as small as 40 μm by 40 μm and with a 40 μmseparation in between.

Based on these current results, as many as 10,000 connections within anarea of 6 mm by 6 mm is achieved. This is satisfactory for currentretinal prosthetic applications.

In certain other aspects, a packaging technology is designed for deviceswith low-density connections. As such, in another embodiment, thepresent invention provides:

-   -   a biocompatible package for low density connections, comprising:    -   a feedthrough layer;    -   an application specific integrated circuit (ASIC) face down on        the feedthrough layer;    -   a printed circuit board (PCB) attached to the ASIC adapted for        off-chip components and wire bonded to the feedthrough layer;    -   metal walls adjacent the feedthrough layer; and a metal lid to        encase and make the biocompatible package.

FIG. 17 shows one embodiment of a low density packaging technology. Asillustrated therein, an ASIC 1735 is placed faced down to connect with afeedthrough layer 1745 (e.g., made of ceramic or other biocompatiblematerial) by flip-chip bonding techniques to make an electricalconnection. Off-chip components 1715 are connected to a PCB 1720 bysoldering or by using conductive epoxy to make an electrical connection.Then, the PCB 1720 is attached to the backside of the ASIC 1735 by anon-conductive epoxy to make a mechanical connection, and wire bonded1725 to the feedthrough layer 1745 (e.g. ceramic) to make an electricalconnection. Solder balls 1740 are used to make an electrical connectionbetween the ASIC 1735 and the feedthrough layer 1745 by flip chipbonding.

Metal walls 1730 a, 1730 b are then hermetically encased with a metallid 1710 by using laser welding techniques. As shown therein, thepackaging has at least two metal walls 1730 a, 1730 b, which arehermetically encased with a feedthrough 1745 by for example, a brazingtechnique.

The unique packaging technique adopts all mature connection and encasingtechnologies (targets to minimize the risk) including flip-chip bonding,wire bonding, brazing, or laser welding. Advantageously, it is designedfor an implanted device with a circuit to survive in corrosive bodyfluids. The design is for 1-100 connections, such as about 1-50, 1-40,1-30, 1-20, 1-10 within a small nanometer or millimeter area. This issatisfactory for current retinal prosthetic applications.

A feedthrough layer 1745 serves as the interface between the enclosedcircuit and a flexible electrode array. The signal can be sent from thecircuit to the electrode array while the circuit can still be wellprotected. The ceramic feedthrough includes vias made of biocompatiblemetals, and the layout of vias can be designed according to the ASIC andother components. A biocompatible metal wall is first encased with thefeedthrough layer by a brazing technique to form a brazing joint. TheASIC is then placed faced down to flip chip bond to the ceramicsubstrate. Other off-chip components 1715 can also be soldered or flipchip bonded to the ceramic substrate. Alternatively, an ASIC and anoff-chip component can stay on the same plane and will occupy more area.

Another preferred option is to first solder or conductive epoxy bondoff-chip components to the PCB. Then, the PCB can be attached on top ofthe ASIC (back side) by a non-conductive epoxy or any glue. Thereafter,an additional wire bonding connection can be made from the PCB toceramic feedthrough to form a complete circuit. In this case (shown inFIG. 17), an ASIC and off-chip components are on different planes tosave surface area.

Advantageously, an enclosed circuit box with a low profile and a smallsurface area is designed. The final step is to hermetically enclose themetal lid 1710 with the metal wall 1730 by laser welding. Before this, avacuum bake treatment is performed to remove moisture or otherimpurities to aid in the hermetic process.

It is understood that the examples and embodiments described herein arefor illustrative purposes only and that various modifications or changesin light thereof will be suggested to persons skilled in the art and areto be included within the spirit and purview of this application andscope of the appended claims. All publications, patents, and patentapplications cited herein are hereby incorporated by reference in theirentirety for all purposes.

1.-10. (canceled)
 11. A biocompatible package for low densityconnections, the biocompatible package comprising: a feedthrough layer;an application specific integrated circuit (ASIC) face down on thefeedthrough layer; a substrate attached to the ASIC adapted for off-chipcomponents and wire bonded to the feedthrough layer; and metal wallsadjacent the feedthrough layer; and a lid to encase and make thebiocompatible package.
 12. The biocompatible package of claim 11,wherein the feedthrough layer is a biocompatible material.
 13. Thebiocompatible package of claim 12, wherein the biocompatible material isceramic.
 14. The biocompatible package of claim 11, wherein thesubstrate is a printed circuit board (PCB).
 15. The biocompatiblepackage of claim 11, wherein the lid is metal.
 16. The biocompatiblepackage of claim 11, wherein an off-chip component is connected to thePCB by soldering or by using conductive epoxy.
 17. The biocompatiblepackage of claim 11, wherein the PCB is attached to the backside of theASIC by a non-conductive epoxy.
 18. The biocompatible package of claim11, wherein the PCB is wire bonded to the feedthrough layer to make anelectrical connection.
 19. The biocompatible package of claim 11,wherein solder balls are used to make an electrical connection betweenthe ASIC and the feedthrough layer.
 20. The biocompatible package ofclaim 11, wherein the metal walls are hermetically encased with a metallid.
 21. The biocompatible package of claim 11, wherein said package isdesigned for low-density connections.
 22. The biocompatible package ofclaim 11, wherein said package has about 1 to about 100 connections in amillimeter area.
 23. The biocompatible package of claim 11, wherein thefeedthrough layer serves as the interface between the enclosed circuitand a flexible electrode array.
 24. The biocompatible package of claim16, wherein an ASIC and off-chip components are on different planes. 25.The biocompatible package of claim 16, wherein an ASIC and off-chipcomponents are on the same plane.
 26. The biocompatible package of claim11, wherein the metal lid and the metal walls are laser welded tohermetically seal.